The present invention relates generally to digital communications systems, and more specifically to a technique for recovering carrier and clock timing for burst signal demodulation.
A synchronous detection technique has been extensively used for demodulating amplitude-phase shift keyed (APSK) signals to take advantage of its relatively high power efficiency by recovering carrier phase and clock (symbol) timing. When the signal is a burst type signal, the carrier and bit timing recovery must be accomplished in a short period of time in response to the arrival of each burst. It is the usual practice to append a preamble containing a carrier recovery sequence and a clock recovery sequence to the header of each burst. The preamble comprises a nonmodulated portion (all 1's or all -1's) for carrier recovery and a modulated portion which is a sequence of alternating 1's and -1's for clock recovery. Since the preamble adds an overhead that tends to decrease the transmission efficiency, or throughput of the digital communication system, it is desired that the length of a preamble be as short as possible.
A technique has been proposed to eliminate the need of a preamble as discussed in "Preambleless Demodulator for Satellite Communications", H. Tomita and J. Namiki, 1989, IEEE (CH2655-9/89/0000-504). According to the proposed technique, a substantial amount of information symbols is required for symbol timing and carrier recovery. To establish synchronization in as short a period of time as possible, very high-speed computation capability is required. Furthermore, at the present state of technology, the proposed system results in costly hardware implementations.